Prediction of hot-carrier degradation in digital CMOS VLSI by timing simulation

E. R. Minami, K. N. Quader, P. K. Ko, Chen-Ming Hu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

We have adapted an RC time-constant based timing simulator to predict hot-carrier degradation effects in digital CMOS circuits. The use of a timing simulator enables a quick characterization of degradation in large circuits. The speed-up over SPICE-based simulation can be greater than 3 orders-of-magnitude.

Original languageEnglish
Title of host publication1992 International Technical Digest on Electron Devices Meeting, IEDM 1992
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages539-542
Number of pages4
ISBN (Electronic)0780308174
DOIs
StatePublished - 1 Jan 1992
Event1992 International Technical Digest on Electron Devices Meeting, IEDM 1992 - San Francisco, United States
Duration: 13 Dec 199216 Dec 1992

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
Volume1992-December
ISSN (Print)0163-1918

Conference

Conference1992 International Technical Digest on Electron Devices Meeting, IEDM 1992
CountryUnited States
CitySan Francisco
Period13/12/9216/12/92

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