Predicting Vt mean and variance from parallel Id measurement with model-fitting technique

Chih Ying Tsai, Kao Chi Lee, Chien Hsueh Lin, Sung Chu Yu, Wen Rong Liau, Alex Chun Liang Hou, Ying Yen Chen, Chun Yi Kuo, Jih Nung Lee, Chia-Tso Chao

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations


To measure the variation of device Vt requires long test for conventional WAT test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of Vt for a large number of DUTs. The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of Vt based on only the combined Id measured from parallel connected DUTs. The experimental results based on the SPICE simulation of a UMC 28nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% R-squared for predicting both of Vt mean and variance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve 42.9X speedup in turn of the required iterations of Id measurement per DUT.

Original languageEnglish
Title of host publicationProceedings - 2016 IEEE 34th VLSI Test Symposium, VTS 2016
PublisherIEEE Computer Society
ISBN (Electronic)9781467384544
StatePublished - 23 May 2016
Event34th IEEE VLSI Test Symposium, VTS 2016 - Las Vegas, United States
Duration: 25 Apr 201627 Apr 2016

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Conference34th IEEE VLSI Test Symposium, VTS 2016
CountryUnited States
CityLas Vegas

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