Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects

Kai Chen*, Chen-Ming Hu, Peng Fang, Min Ren Lin, Donald L. Wollesen, Associate

*Corresponding author for this work

Research output: Contribution to journalArticle

53 Scopus citations

Abstract

Sub-quarter micron MOSFET's and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5-3.3 V. Idsat can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thicknesses for different interconnect loading are highlighted.

Original languageEnglish
Pages (from-to)1951-1957
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume44
Issue number11
DOIs
StatePublished - 1 Dec 1997

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