Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects

Kai Chen; Chen-Ming Hu; Peng Fang; Min Ren Lin; Donald L. Wollesen; Associate

doi:10.1109/16.641365

Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects

Kai Chen^*, Chen-Ming Hu, Peng Fang, Min Ren Lin, Donald L. Wollesen, Associate

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Contribution to journal › Article

53 Scopus citations

Abstract

Sub-quarter micron MOSFET's and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5-3.3 V. Idsat can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thicknesses for different interconnect loading are highlighted.

Original language	English
Pages (from-to)	1951-1957
Number of pages	7
Journal	IEEE Transactions on Electron Devices
Volume	44
Issue number	11
DOIs	https://doi.org/10.1109/16.641365
State	Published - 1 Dec 1997

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abstract = "Sub-quarter micron MOSFET's and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5-3.3 V. Idsat can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thicknesses for different interconnect loading are highlighted.",

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N2 - Sub-quarter micron MOSFET's and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5-3.3 V. Idsat can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thicknesses for different interconnect loading are highlighted.

AB - Sub-quarter micron MOSFET's and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5-3.3 V. Idsat can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thicknesses for different interconnect loading are highlighted.

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