Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects

Kai Chen; Chen-Ming Hu; Peng Fang; Min Ren Lin; Donald L. Wollesen; Associate

doi:10.1109/16.641365

Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects

Kai Chen^*, Chen-Ming Hu, Peng Fang, Min Ren Lin, Donald L. Wollesen, Associate

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Contribution to journal › Article › peer-review

53 Scopus citations

Abstract

Sub-quarter micron MOSFET's and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5-3.3 V. Idsat can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thicknesses for different interconnect loading are highlighted.

Original language	English
Pages (from-to)	1951-1957
Number of pages	7
Journal	IEEE Transactions on Electron Devices
Volume	44
Issue number	11
DOIs	https://doi.org/10.1109/16.641365
State	Published - 1 Dec 1997

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@article{4a28f65bcce6473b954cbeb94786a7b7,

title = "Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects",

abstract = "Sub-quarter micron MOSFET's and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5-3.3 V. Idsat can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thicknesses for different interconnect loading are highlighted.",

author = "Kai Chen and Chen-Ming Hu and Peng Fang and Lin, {Min Ren} and Wollesen, {Donald L.} and Associate",

year = "1997",

month = dec,

day = "1",

doi = "10.1109/16.641365",

language = "English",

volume = "44",

pages = "1951--1957",

journal = "Ieee Transactions On Electron Devices",

issn = "0018-9383",

publisher = "IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC",

number = "11",

}

TY - JOUR

T1 - Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects

AU - Chen, Kai

AU - Hu, Chen-Ming

AU - Fang, Peng

AU - Lin, Min Ren

AU - Wollesen, Donald L.

AU - Associate,

PY - 1997/12/1

Y1 - 1997/12/1

N2 - Sub-quarter micron MOSFET's and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5-3.3 V. Idsat can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thicknesses for different interconnect loading are highlighted.

AB - Sub-quarter micron MOSFET's and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5-3.3 V. Idsat can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thicknesses for different interconnect loading are highlighted.

UR - http://www.scopus.com/inward/record.url?scp=0031275325&partnerID=8YFLogxK

U2 - 10.1109/16.641365

DO - 10.1109/16.641365

M3 - Article

AN - SCOPUS:0031275325

VL - 44

SP - 1951

EP - 1957

JO - Ieee Transactions On Electron Devices

JF - Ieee Transactions On Electron Devices

SN - 0018-9383

IS - 11

ER -

Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects

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