Power-switch gate-oxide breakdown tolerance techniques for power-gated SRAM

Hao I. Yang; Ching Te Chuang; Wei Hwang

doi:10.1109/ICICDT.2010.5510278

Power-switch gate-oxide breakdown tolerance techniques for power-gated SRAM

Hao I. Yang^*, Ching Te Chuang, Wei Hwang

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

The gate-oxide breakdowns (BD) of the power-switches have severe and even detrimental effects on the margin, stability, and performance of the power-gated SRAM. This paper proposes and evaluates several techniques to mitigate the power-switch gate-oxide BD, including adding a gate series resistance to the power switch, dual threshold voltage power switch, thick gate-oxide power switch, and dual gate-oxide thickness power switch. It is shown that dual gate-oxide thickness power switch improves the time-to-dielectric-breakdown of the power switch while maintaining the performance without side effect.

Original language	English
Title of host publication	2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010
Pages	102-105
Number of pages	4
DOIs	https://doi.org/10.1109/ICICDT.2010.5510278
State	Published - 20 Aug 2010
Event	2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010 - Grenoble, France Duration: 2 Jun 2010 → 4 Jun 2010

Publication series

Name	2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010

Conference

Conference	2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010
Country	France
City	Grenoble
Period	2/06/10 → 4/06/10

Keywords

Gate-oxide breakdown
Power gating technology
SRAM

Access to Document

10.1109/ICICDT.2010.5510278

Link to publication in Scopus

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Yang, H. I., Chuang, C. T., & Hwang, W. (2010). Power-switch gate-oxide breakdown tolerance techniques for power-gated SRAM. In 2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010 (pp. 102-105). [5510278] (2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010). https://doi.org/10.1109/ICICDT.2010.5510278

@inproceedings{fdf33361e8284fa19d9844487661f50a,

title = "Power-switch gate-oxide breakdown tolerance techniques for power-gated SRAM",

abstract = "The gate-oxide breakdowns (BD) of the power-switches have severe and even detrimental effects on the margin, stability, and performance of the power-gated SRAM. This paper proposes and evaluates several techniques to mitigate the power-switch gate-oxide BD, including adding a gate series resistance to the power switch, dual threshold voltage power switch, thick gate-oxide power switch, and dual gate-oxide thickness power switch. It is shown that dual gate-oxide thickness power switch improves the time-to-dielectric-breakdown of the power switch while maintaining the performance without side effect.",

keywords = "Gate-oxide breakdown, Power gating technology, SRAM",

author = "Yang, {Hao I.} and Chuang, {Ching Te} and Wei Hwang",

year = "2010",

month = aug,

day = "20",

doi = "10.1109/ICICDT.2010.5510278",

language = "English",

isbn = "9781424457748",

series = "2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010",

pages = "102--105",

booktitle = "2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010",

note = "null ; Conference date: 02-06-2010 Through 04-06-2010",

}

Yang, HI, Chuang, CT & Hwang, W 2010, Power-switch gate-oxide breakdown tolerance techniques for power-gated SRAM. in 2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010., 5510278, 2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010, pp. 102-105, 2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010, Grenoble, France, 2/06/10. https://doi.org/10.1109/ICICDT.2010.5510278

Power-switch gate-oxide breakdown tolerance techniques for power-gated SRAM. / Yang, Hao I.; Chuang, Ching Te; Hwang, Wei.

2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010. 2010. p. 102-105 5510278 (2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Power-switch gate-oxide breakdown tolerance techniques for power-gated SRAM

AU - Yang, Hao I.

AU - Chuang, Ching Te

AU - Hwang, Wei

PY - 2010/8/20

Y1 - 2010/8/20

N2 - The gate-oxide breakdowns (BD) of the power-switches have severe and even detrimental effects on the margin, stability, and performance of the power-gated SRAM. This paper proposes and evaluates several techniques to mitigate the power-switch gate-oxide BD, including adding a gate series resistance to the power switch, dual threshold voltage power switch, thick gate-oxide power switch, and dual gate-oxide thickness power switch. It is shown that dual gate-oxide thickness power switch improves the time-to-dielectric-breakdown of the power switch while maintaining the performance without side effect.

AB - The gate-oxide breakdowns (BD) of the power-switches have severe and even detrimental effects on the margin, stability, and performance of the power-gated SRAM. This paper proposes and evaluates several techniques to mitigate the power-switch gate-oxide BD, including adding a gate series resistance to the power switch, dual threshold voltage power switch, thick gate-oxide power switch, and dual gate-oxide thickness power switch. It is shown that dual gate-oxide thickness power switch improves the time-to-dielectric-breakdown of the power switch while maintaining the performance without side effect.

KW - Gate-oxide breakdown

KW - Power gating technology

KW - SRAM

UR - http://www.scopus.com/inward/record.url?scp=77955635475&partnerID=8YFLogxK

U2 - 10.1109/ICICDT.2010.5510278

DO - 10.1109/ICICDT.2010.5510278

M3 - Conference contribution

AN - SCOPUS:77955635475

SN - 9781424457748

T3 - 2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010

SP - 102

EP - 105

BT - 2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010

Y2 - 2 June 2010 through 4 June 2010

ER -