TY - GEN
T1 - Power-switch gate-oxide breakdown tolerance techniques for power-gated SRAM
AU - Yang, Hao I.
AU - Chuang, Ching Te
AU - Hwang, Wei
PY - 2010/8/20
Y1 - 2010/8/20
N2 - The gate-oxide breakdowns (BD) of the power-switches have severe and even detrimental effects on the margin, stability, and performance of the power-gated SRAM. This paper proposes and evaluates several techniques to mitigate the power-switch gate-oxide BD, including adding a gate series resistance to the power switch, dual threshold voltage power switch, thick gate-oxide power switch, and dual gate-oxide thickness power switch. It is shown that dual gate-oxide thickness power switch improves the time-to-dielectric-breakdown of the power switch while maintaining the performance without side effect.
AB - The gate-oxide breakdowns (BD) of the power-switches have severe and even detrimental effects on the margin, stability, and performance of the power-gated SRAM. This paper proposes and evaluates several techniques to mitigate the power-switch gate-oxide BD, including adding a gate series resistance to the power switch, dual threshold voltage power switch, thick gate-oxide power switch, and dual gate-oxide thickness power switch. It is shown that dual gate-oxide thickness power switch improves the time-to-dielectric-breakdown of the power switch while maintaining the performance without side effect.
KW - Gate-oxide breakdown
KW - Power gating technology
KW - SRAM
UR - http://www.scopus.com/inward/record.url?scp=77955635475&partnerID=8YFLogxK
U2 - 10.1109/ICICDT.2010.5510278
DO - 10.1109/ICICDT.2010.5510278
M3 - Conference contribution
AN - SCOPUS:77955635475
SN - 9781424457748
T3 - 2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010
SP - 102
EP - 105
BT - 2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010
Y2 - 2 June 2010 through 4 June 2010
ER -