Power-switch gate-oxide breakdown tolerance techniques for power-gated SRAM

Hao I. Yang*, Ching Te Chuang, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

The gate-oxide breakdowns (BD) of the power-switches have severe and even detrimental effects on the margin, stability, and performance of the power-gated SRAM. This paper proposes and evaluates several techniques to mitigate the power-switch gate-oxide BD, including adding a gate series resistance to the power switch, dual threshold voltage power switch, thick gate-oxide power switch, and dual gate-oxide thickness power switch. It is shown that dual gate-oxide thickness power switch improves the time-to-dielectric-breakdown of the power switch while maintaining the performance without side effect.

Original languageEnglish
Title of host publication2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010
Pages102-105
Number of pages4
DOIs
StatePublished - 20 Aug 2010
Event2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010 - Grenoble, France
Duration: 2 Jun 20104 Jun 2010

Publication series

Name2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010

Conference

Conference2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010
CountryFrance
CityGrenoble
Period2/06/104/06/10

Keywords

  • Gate-oxide breakdown
  • Power gating technology
  • SRAM

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