Power-rail ESD clamp circuit with ultralow standby leakage current and high area efficiency in nanometer CMOS technology

Chih Ting Yeh*, Ming-Dou Ker

*Corresponding author for this work

Research output: Contribution to journalArticle

7 Scopus citations

Abstract

An ultralow-leakage power-rail electrostatic discharge (ESD) clamp circuit realized with only thin gate oxide devices and with silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. By reducing the voltage difference across the gate oxide of the devices in the ESD detection circuit, the proposed power-rail ESD clamp circuit can achieve an ultralow standby leakage current. In addition, the ESD-transient detection circuit can be totally embedded in the SCR device by modifying the layout structure. From the measured results, the proposed power-rail ESD clamp circuit with an SCR width of 45 μm can achieve 7-kV human-body-model and 350-V machine-model ESD levels under the ESD stress event while consuming only a standby leakage current in the order of nanoamperes at room temperature under the normal circuit operating condition with 1-V bias.

Original languageEnglish
Article number6269072
Pages (from-to)2626-2634
Number of pages9
JournalIEEE Transactions on Electron Devices
Volume59
Issue number10
DOIs
StatePublished - 21 Aug 2012

Keywords

  • gate leakage
  • power-rail electrostatic discharge (ESD) clamp circuit
  • silicon-controlled rectifier (SCR)

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