Power-planning-aware soft error hardening via selective voltage assignment

Kai-Chiang Wu, Diana Marculescu

Research output: Contribution to journalArticle

4 Scopus citations

Abstract

Soft errors, which have been a significant concern in memories, are now a main factor in reliability degradation of logic circuits. This paper presents a power-planning-aware methodology using dual supply voltages for soft error hardening. Given a constraint on power overhead, our proposed framework can minimize the soft error rate (SER) of a circuit via selective voltage assignment. In the 70-nm predictive technology model, circuit SER can be reduced by 23% on top of SER-aware gate resizing. For power-planning awareness, a bi-partitioning technique based on a simplified version of the Fiduccia-Mattheyses (FM) algorithm is presented. The simplified FM-based partitioning refines the result of selective voltage assignment by decreasing the number of connections across voltage islands, while maintaining the SER reduction that has been accomplished.

Original languageEnglish
Article number6421010
Pages (from-to)136-145
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume22
Issue number1
DOIs
StatePublished - 1 Jan 2014

Keywords

  • Partitioning
  • reliability
  • soft error rate (SER)
  • soft errors
  • voltage assignment

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