Power optimization for clock network with clock gate cloning and flip-flop merging

Shih Chuan Lo, Chih Cheng Hsu, Po-Hung Lin

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

10 Scopus citations

Abstract

Applying clock gates (CGs) and multi-bit flip-flops (MBFFs) are two of the most effective techniques for low power clock network design. Some previous works had proposed to optimize clock network with either CGs or MBFFs, but none of them simultaneously considers both CGs and MBFFs during clock network optimization. Although CGs and MBFFs can be optimized separately, the resulting dynamic power may not be optimal. This paper presents the first problem formulation in the literature for gated clock network optimization with simultaneous CG cloning and FF merging. To effectively solve the problem, a novel optimization flow consisting of MBFF-aware CG cloning, CG-based FF merging, and MBFF and CG placement optimization is introduced. Experimental results show that the proposed flow results in better dynamic power and clock wirelength compared with other flows which optimize gated clock network with CGs and MBFFs separately.

Original languageEnglish
Title of host publicationISPD 2014 - Proceedings of the 2014 ACM International Symposium on Physical Design
PublisherAssociation for Computing Machinery
Pages77-83
Number of pages7
ISBN (Print)9781450325929
DOIs
StatePublished - 1 Jan 2014
Event2014 ACM International Symposium on Physical Design, ISPD 2014 - Petaluma, CA, United States
Duration: 30 Mar 20142 Apr 2014

Publication series

NameProceedings of the International Symposium on Physical Design

Conference

Conference2014 ACM International Symposium on Physical Design, ISPD 2014
CountryUnited States
CityPetaluma, CA
Period30/03/142/04/14

Keywords

  • Clock gating
  • Clock network
  • Multi-bit flip-flop
  • Power optimization

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