Power gating technique for embedded pseudo SRAM

Ching Yun Cheng*, Ming Hung Chang, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

In this paper, we deploy power gating technique on a low-power Pseudo SRAM circuit with 3T1D gain cell. A 256-word × 32-BL-pair 3T1D gain cell array is implemented in standard logic technology with TSMC 0.13um model for multi-bank Pseudo SRAM. Each Pseudo SRAM has its independent access control unit, enabling parallel refresh and read-write accesses to different bank. By employing power gating technique in sense amplifier of 3T1D gain cell array, 15% standby leakage current: during sleep mode could be reduced. Also, 12% sensing speed could be enhanced when Pseudo SRAM is operated in normal mode (simulated with TSMC 100nm technology model).

Original languageEnglish
Title of host publication2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
DOIs
StatePublished - 28 Sep 2007
Event2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Hsinchu, Taiwan
Duration: 25 Apr 200727 Apr 2007

Publication series

Name2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

Conference

Conference2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
CountryTaiwan
CityHsinchu
Period25/04/0727/04/07

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  • Cite this

    Cheng, C. Y., Chang, M. H., & Hwang, W. (2007). Power gating technique for embedded pseudo SRAM. In 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers [4239443] (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2007.373251