Power-aware soft error hardening via selective voltage scaling

Kai-Chiang Wu, Diana Marculescu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Scopus citations

Abstract

Nanoscale integrated circuits are becoming increasingly sensitive to radiation-induced transient faults (soft errors) due to current technology scaling trends, such as shrinking feature sizes and reducing supply voltages. Soft errors, which have been a significant concern in memories, are now a main factor in reliability degradation of logic circuits. This paper presents a power-aware methodology using dual supply voltages for soft error hardening. Given a constraint on power overhead, our proposed framework can minimize the soft error rate (SER) of a circuit via selective voltage scaling. On average, circuit SER can be reduced by 33.45% for various sizes of transient glitches with only 11.74% energy increase. The overhead in normalized power-delay-area product per 1% SER reduction is 0.64%, 1.33X less than that of existing state-of-the-art approaches.

Original languageEnglish
Title of host publication26th IEEE International Conference on Computer Design 2008, ICCD
Pages301-306
Number of pages6
DOIs
StatePublished - 1 Dec 2008
Event26th IEEE International Conference on Computer Design 2008, ICCD - Lake Tahoe, CA, United States
Duration: 12 Oct 200815 Oct 2008

Publication series

Name26th IEEE International Conference on Computer Design 2008, ICCD

Conference

Conference26th IEEE International Conference on Computer Design 2008, ICCD
CountryUnited States
CityLake Tahoe, CA
Period12/10/0815/10/08

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    Wu, K-C., & Marculescu, D. (2008). Power-aware soft error hardening via selective voltage scaling. In 26th IEEE International Conference on Computer Design 2008, ICCD (pp. 301-306). [4751877] (26th IEEE International Conference on Computer Design 2008, ICCD). https://doi.org/10.1109/ICCD.2008.4751877