Power and substrate noise tolerance of configurable embedded memories in SoC

Meng Fan Chang*, Kuei-Ann Wen

*Corresponding author for this work

Research output: Contribution to journalArticle

4 Scopus citations

Abstract

When subject to various power and substrate noise, configurable embedded memories in multimedia SoCs are importantly affected with pattern-dependant soft failures. This work investigates the effects of such failures on memory cells, arrays and circuit design. The ground bounce reduces the memory cell current more than the supply voltage drop or the substrate bias dip. A noise track-and-filter (NTAF) architecture, which is a self-timed architecture with specific layout patterns, is presented to provide the required timing relaxation, while minimizing the speed degradation. This NTAF method provides greater noise tolerance and design for manufacturing (DFM) capability. Configurable embedded SRAM and ROM in 0.18 μ m CMOS process are studied.

Original languageEnglish
Pages (from-to)81-91
Number of pages11
JournalJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Volume41
Issue number1
DOIs
StatePublished - 1 Aug 2005

Keywords

  • ROM
  • SRAM
  • Substrate noise
  • Supply noise

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