Post-placement power optimization with multi-bit flip-flops

Yao Tsung Chang*, Chih Cheng Hsu, Po-Hung Lin, Yu Wen Tsai, Sheng Fong Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

51 Scopus citations

Abstract

Optimization for power is always one of the most important design objectives in modern nanometer IC design. Recent studies have shown the effectiveness of applying multi-bit flip-flops to save the power consumption of the clock network. However, all the previous works applied multi-bit flip-flops at earlier design stages, which could be very difficult to carry out the trade-off among power, timing, and other design objectives. This paper presents a novel power optimization method by incrementally applying more multi-bit flip-flops at the post-placement stage to gain more clock power saving while considering the placement density and timing slack constraints, and simultaneously minimizing interconnecting wirelength. Experimental results based on the industry benchmark circuits show that our approach is very effective and efficient, which can be seamlessly integrated in modern design flow.

Original languageEnglish
Title of host publication2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010
Pages218-223
Number of pages6
DOIs
StatePublished - 1 Dec 2010
Event2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010 - San Jose, CA, United States
Duration: 7 Nov 201011 Nov 2010

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)1092-3152

Conference

Conference2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010
CountryUnited States
CitySan Jose, CA
Period7/11/1011/11/10

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