Positive bias and temperature stress induced two-stage drain current degradation in HfSiON nMOSFET's

C. T. Chan*, C. J. Tang, Ta-Hui Wang, H. C.H. Wang, D. D. Tang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

Positive bias and temperature (PBTI) stress induced drain current degradation in HfSiON gate dielectric nMOSFETs is investigated by using a transient measurement technique. The degradation exhibits two stages, featuring different degradation rate and stress temperature dependence. The drain current degradation in the first stage is attributed to the charging of pre-existing high-k dielectric traps while the degradation in the second stage is mainly due to additional high-k trap creation. Process effect on high-k trap growth is evaluated.

Original languageEnglish
Title of host publicationIEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest
Pages563-566
Number of pages4
DOIs
StatePublished - 1 Dec 2005
EventIEEE International Electron Devices Meeting, 2005 IEDM - Washington, DC, MD, United States
Duration: 5 Dec 20057 Dec 2005

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
Volume2005
ISSN (Print)0163-1918

Conference

ConferenceIEEE International Electron Devices Meeting, 2005 IEDM
CountryUnited States
CityWashington, DC, MD
Period5/12/057/12/05

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    Chan, C. T., Tang, C. J., Wang, T-H., Wang, H. C. H., & Tang, D. D. (2005). Positive bias and temperature stress induced two-stage drain current degradation in HfSiON nMOSFET's. In IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest (pp. 563-566). [1609408] (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2005). https://doi.org/10.1109/IEDM.2005.1609408