Reuse of System-on-Chip (SoC) verification stimuli across various design models is a challenging problem. However, if used effectively, it significantly reduces verification time and quickly increases confidence in the robustness of a design. We use pseudo-random stimuli to drive tests on an SoC using simulation BFMs and reuse them on emulation-BFMs. Initial results on a Power Architecture™ Technology-based SoC demonstrate about a 100x speedup on the emulator vis-á-vis the simulator.
|Title of host publication||International Test Conference, ITC 2009 - Proceedings|
|State||Published - 15 Dec 2009|
|Event||International Test Conference, ITC 2009 - Austin, TX, United States|
Duration: 1 Nov 2009 → 6 Nov 2009
|Name||Proceedings - International Test Conference|
|Conference||International Test Conference, ITC 2009|
|Period||1/11/09 → 6/11/09|