Portable simulation/emulation stimulus on an industrial-strength SoC

Francisco Torres*, Rohit Srivastava, Javier Ruiz, H. P. Wen, Mrinal Bose, Jayanta Bhadra

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Reuse of System-on-Chip (SoC) verification stimuli across various design models is a challenging problem. However, if used effectively, it significantly reduces verification time and quickly increases confidence in the robustness of a design. We use pseudo-random stimuli to drive tests on an SoC using simulation BFMs and reuse them on emulation-BFMs. Initial results on a Power Architecture™ Technology-based SoC demonstrate about a 100x speedup on the emulator vis-á-vis the simulator.

Original languageEnglish
Title of host publicationInternational Test Conference, ITC 2009 - Proceedings
DOIs
StatePublished - 15 Dec 2009
EventInternational Test Conference, ITC 2009 - Austin, TX, United States
Duration: 1 Nov 20096 Nov 2009

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539

Conference

ConferenceInternational Test Conference, ITC 2009
CountryUnited States
CityAustin, TX
Period1/11/096/11/09

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