PolySi- SiO2 - ZrO2 - SiO2 -Si flash memory incorporating a sol-gel-derived ZrO2 charge trapping layer

Tzu Hsiang Hsu*, Hsin Chiang You, Fu-Hsiang Ko, Tan Fu Lei

*Corresponding author for this work

Research output: Contribution to journalArticle

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Abstract

In this paper, we propose a method for depositing the charge trapping layer of a high- k polySi- SiO2 - ZrO2 - SiO2 -Si (SOZOS) memory device. In this approach, the trapping layer was formed through simple two steps: (i) spin-coating of the ZrCl4 precursor and (ii) rapid thermal annealing for 1 min at 900°C under an oxygen atmosphere. The morphology of the ZrO2 charge trapping layer was confirmed through X-ray photoemission spectroscopy analysis. The sol-gel-derived layer exhibited improved charge trapping in the SOZOS memory device, resulting in a threshold voltage shift of 2.7 V in the Id - Vg curve, PE (program/erase) speeds as fast as 0.1 ms, good data retention up to 104 s (only a 5% charge loss due to deep trapping in the ZrO2 layer), and good endurance (no memory window narrowing after 105 PE cycles).

Original languageEnglish
Article number030611JES
JournalJournal of the Electrochemical Society
Volume153
Issue number11
DOIs
StatePublished - 17 Oct 2006

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