PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit

Chih Ting Yeh*, Yung Chih Liang, Ming-Dou Ker

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

A new power-rail ESD clamp circuit designed with PMOS as main ESD clamp device has been proposed and verified in a 65nm 1.2V CMOS process. The new proposed design with adjustable holding voltage controlled by the ESD detection circuit has better immunity against mis-trigger or transient-induced latch-on event. The layout area and the standby leakage current of this new proposed design are much superior to that of traditional RC-based power-rail ESD clamp circuit with NMOS as main ESD clamp device.

Original languageEnglish
Title of host publicationElectrical Overstress/Electrostatic Discharge Symposium Proceedings - 2011, EOS/ESD 2011
StatePublished - 10 Nov 2011
Event2011 33rd Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2011 - Anaheim, CA, United States
Duration: 11 Sep 201116 Sep 2011

Publication series

NameElectrical Overstress/Electrostatic Discharge Symposium Proceedings
ISSN (Print)0739-5159

Conference

Conference2011 33rd Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2011
CountryUnited States
CityAnaheim, CA
Period11/09/1116/09/11

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