A new power-rail ESD clamp circuit designed with PMOS as main ESD clamp device has been proposed and verified in a 65nm 1.2V CMOS process. The new proposed design with adjustable holding voltage controlled by the ESD detection circuit has better immunity against mis-trigger or transient-induced latch-on event. The layout area and the standby leakage current of this new proposed design are much superior to that of traditional RC-based power-rail ESD clamp circuit with NMOS as main ESD clamp device.
|Title of host publication||Electrical Overstress/Electrostatic Discharge Symposium Proceedings - 2011, EOS/ESD 2011|
|State||Published - 10 Nov 2011|
|Event||2011 33rd Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2011 - Anaheim, CA, United States|
Duration: 11 Sep 2011 → 16 Sep 2011
|Name||Electrical Overstress/Electrostatic Discharge Symposium Proceedings|
|Conference||2011 33rd Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2011|
|Period||11/09/11 → 16/09/11|