PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit

Chih Ting Yeh*, Ming-Dou Ker

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

A new power-rail ESD clamp circuit designed with PMOS as main ESD clamp device has been proposed and verified in a 65 nm 1.2 V CMOS process. The new proposed design with adjustable holding voltage controlled by the ESD detection circuit has better immunity against mis-trigger or transient-induced latch-on event. The layout area and the standby leakage current of this new proposed design are much superior to that of traditional RC-based power-rail ESD clamp circuit with NMOS as main ESD clamp device.

Original languageEnglish
Pages (from-to)208-214
Number of pages7
JournalMicroelectronics Reliability
Volume53
Issue number2
DOIs
StatePublished - 1 Feb 2013

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