Platform based deisign of all binary motion estimation (ABME) with bus interleaved architecture

Shih Hao Wang, Wei Lun Tao, Chung Neng Wang, Wen-Hsiao Peng, Tihao Chiang*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

This paper presents an efficient hardware-software implementation with a marcoblock based pipelining and a bus interlaced architecture for all binary motion estimation (ABME), which has been proven to be simple and low cost for hardware design. The bus interleaved preprocessing module of the ABME architecture can generate downsampling and binarized data in the same flow without additional dedicated hardware. With the 3layer binary bitplane of ABME, we use a two-dimensional (2-D) mapping unit and a binary adder tree instead of a systolic array to compute the block matching metric, which is sum of difference (SoD), in one cycle. In addition, a new bus bandwidth reduction scheme is proposed by reusing the binarized image, which can achieve up to 67% bus bandwidth saving. The experiment shows that for each macroblock, our design can finish ABME within 283 cycles with 65k gate counts synthesized by UMC 0.18um cell library.

Original languageEnglish
Title of host publication2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Pages241-244
Number of pages4
DOIs
StatePublished - 1 Dec 2005
Event2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT) - Hsinchu, Taiwan
Duration: 27 Apr 200529 Apr 2005

Publication series

Name2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Volume2005

Conference

Conference2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
CountryTaiwan
CityHsinchu
Period27/04/0529/04/05

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