PLANE: A new ATPG system for PLAs

Juinn-Dar Huang, W. Z. Shen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, a new PLA ATPG system PLANE is presented. PLANE uses the depth-first sharp operation for efficient test generation. Besides, a powerful test compaction technique using the intersection buffer is applied to get a more compact test set. PLANE also uses parallel fault simulation and backend fault simulation to exploit its performance. Experimental results show that the test length of PLANE is 7.5% shorter than that of PLATYPUS.

Original languageEnglish
Title of host publicationATS 1993 Proceedings - 2nd Asian Test Symposium
PublisherIEEE Computer Society
Pages107-112
Number of pages6
ISBN (Electronic)081863930X
DOIs
StatePublished - 1 Jan 1993
Event2nd IEEE Asian Test Symposium, ATS 1993 - Beijing, China
Duration: 16 Nov 199318 Nov 1993

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735

Conference

Conference2nd IEEE Asian Test Symposium, ATS 1993
CountryChina
CityBeijing
Period16/11/9318/11/93

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  • Cite this

    Huang, J-D., & Shen, W. Z. (1993). PLANE: A new ATPG system for PLAs. In ATS 1993 Proceedings - 2nd Asian Test Symposium (pp. 107-112). [398788] (Proceedings of the Asian Test Symposium). IEEE Computer Society. https://doi.org/10.1109/ATS.1993.398788