Planar junctionless poly-Si thin-film transistors with single gate and double gate

Chia Hsin Chou*, I. Che Lee, Dai Che Lei, Huang-Chung Cheng

*Corresponding author for this work

Research output: Contribution to journalArticle

3 Scopus citations

Abstract

In this letter, single- and double-gate (SG and DG) planar junctionless (JL) thin-film transistors fabricated via a simple process with an in situ-doped active layer is discussed. The DG structure demonstrated a superior subthreshold swing of 160mV/dec and a lower off-current of 1.3 × 10 -13A than those of 329mV/dec and 2.1 × 10-12A for the SG structure, respectively. It contributes to the enhancement of the gate controllability and ultrathin channel. Consequently, the simple fabrication process of the DG JL device is suitable for future application on system-on-panel and three-dimensional integrated circuits.

Original languageEnglish
Article number06JE07
JournalJapanese Journal of Applied Physics
Volume53
Issue number6 SPEC. ISSUE
DOIs
StatePublished - 1 Jan 2014

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