Pipelined arithmetic encoder design for lossless JPEG XR encoder

Ching Yen Chien*, Sheng-Chieh Huang, Chia Ho Pan, Ce Min Fang, Liang Gee Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

With rapid progress of sensors, display devices, and computing engines, image application exists everywhere. High quality, high compression rates of digital image and low computational cost are important factors of consumer electronics. In this paper, we proposed a 4:4:4 lossless JPEG XR encoder design. In JPEG XR encoder, entropy coding is a critical module of encoder. We proposed a well-defined timing schedule of pipeline architecture to speed up the entropy encoding, which is the most computationally intensive part in JPEG XR encoder. This design can be used for the digital photography applications to achieve the low complexity of computation, low storage, and high dynamic range.

Original languageEnglish
Title of host publication2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009
Pages144-147
Number of pages4
DOIs
StatePublished - 27 Oct 2009
Event2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009 - Kyoto, Japan
Duration: 25 May 200928 May 2009

Publication series

NameDigest of Technical Papers - IEEE International Conference on Consumer Electronics
ISSN (Print)0747-668X

Conference

Conference2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009
CountryJapan
CityKyoto
Period25/05/0928/05/09

Keywords

  • ASIC
  • Encoder
  • HD-photo
  • JPEG XR

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