Pin accessibility evaluating model for improving routability of VLSI designs

Hong Yan Su, Shinichi Nishizawa, Yan Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Pin accessibility influences the routability of a design at the stage of block/chip assembling. The estimation model for pin accessibility in previous researches counts the total number of intersections between each pin and M2 routing tracks. It does not consider the variation of pin accessibility as the spacing between a pin and its neighboring pins and metal wires changes. Besides, it cannot properly deal with the off-grid pin access neither. In this paper, we propose a general model for pin accessibility estimation. In the model, all directions to connect to the boundary of a pin are under estimation. Off-grid pin access is also available. Experimental results show that the reduction rate of minimum area to complete the routing of a circuit can be 7.0% on average. Due to the diminishment of required area for routing, the total number of vias for higher metal layer also decrease under the same area constraint.

Original languageEnglish
Title of host publicationProceedings - 30th IEEE International System on Chip Conference, SOCC 2017
EditorsJurgen Becker, Ramalingam Sridhar, Hai Li, Ulf Schlichtmann, Massimo Alioto
PublisherIEEE Computer Society
Pages56-61
Number of pages6
ISBN (Electronic)9781538640333
DOIs
StatePublished - 18 Dec 2017
Event30th IEEE International System on Chip Conference, SOCC 2017 - Munich, Germany
Duration: 5 Sep 20178 Sep 2017

Publication series

NameInternational System on Chip Conference
Volume2017-September
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Conference

Conference30th IEEE International System on Chip Conference, SOCC 2017
CountryGermany
CityMunich
Period5/09/178/09/17

Keywords

  • Block routing
  • Cell layout design
  • Pin accessibility
  • Routability

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  • Cite this

    Su, H. Y., Nishizawa, S., Wu, Y. S., Shiomi, J., Li, Y-L., & Onodera, H. (2017). Pin accessibility evaluating model for improving routability of VLSI designs. In J. Becker, R. Sridhar, H. Li, U. Schlichtmann, & M. Alioto (Eds.), Proceedings - 30th IEEE International System on Chip Conference, SOCC 2017 (pp. 56-61). (International System on Chip Conference; Vol. 2017-September). IEEE Computer Society. https://doi.org/10.1109/SOCC.2017.8226007