Physically-based built-in spice poly-Si TFT model for circuit simulation and reliability evaluation

Steve S. Chung*, Darren C. Chen, C. T. Cheng, C. F. Yeh

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

14 Scopus citations


A Poly-Si TFT model for circuit simulation in Spice is presented, combined with a device degradation model for the first time to evaluate the circuit reliability. Both I-V and C-V models for the whole device operating regime have been developed. In the I-V model, emphasis has been taken to derive the mobility degradation induced by the grain boundary potential barrier height and trap density. The small geometry effect, off-state current and the parasitic BJT effect are also considered in the model. Good agreements between modeled and experimental data were achieved. To evaluate the circuit reliability after electrical stress, the device reliability model has also been developed. Finally, simulation a 27-stage ring oscillator has been demonstrated, which shows delay time of about 1nsec per stage.

Original languageEnglish
Article number5552459
Pages (from-to)139-142
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
StatePublished - 1 Dec 1996
EventProceedings of the 1996 IEEE International Electron Devices Meeting - San Francisco, CA, USA
Duration: 8 Dec 199611 Dec 1996

Fingerprint Dive into the research topics of 'Physically-based built-in spice poly-Si TFT model for circuit simulation and reliability evaluation'. Together they form a unique fingerprint.

Cite this