Physical mechanism and device simulation on transient-induced latchup in CMOS ICs under system-level ESD test

Ming-Dou Ker*, Sheng Fu Hsu

*Corresponding author for this work

Research output: Contribution to journalArticle

52 Scopus citations

Abstract

The physical mechanism of transient-induced latchup (TLU) in CMOS ICs under the system-level electrostatic discharge (ESD) test is clearly characterized by device simulation and experimental verification in time domain. For TLU characterization, an underdamped sinusoidal voltage stimulus has been clarified as the realistic TLU-triggering stimulus under the system-level ESD test. The specific "sweep-back" current caused by the minority carriers stored within the parasitic pnpn structure of CMOS ICs has been qualitatively proved to be the major cause of TLU. All the simulation results on TLU have been practically verified in silicon with test chips fabricated by 0.25-μm CMOS technology.

Original languageEnglish
Pages (from-to)1821-1831
Number of pages11
JournalIEEE Transactions on Electron Devices
Volume52
Issue number8
DOIs
StatePublished - 1 Aug 2005

Keywords

  • Holding voltage
  • Latchup
  • Silicon controlled rectifier (SCR)
  • System-level electrostatic discharge (ESD) test
  • Transient-induced latchup (TLU)

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