Performance validation of dynamic-remapping-based task scheduling on 3D multi-core processors

Chien Hui Liao*, Hung Pin Wen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Many heuristics applying Dynamic Voltage and Frequency Scaling (DVFS) techniques have been proposed for energy minimization on three-dimensional multi-core processors. However, most previous works were built upon a fixed task-to-core mapping where many slack spaces can be further improved. In our previous research, we proposed a dynamic remapping strategy, Iterative Dynamic Remapping (IDR), to enhance an energy-aware task-scheduling algorithm while considering transmission cost. In this paper, performance for IDR with consideration to transmission costs between cores is validated through comparison with a Quadratic-Programming-based (QP-based) method and a Genetic-Algorithm-based (GA-based) method. Experimental results show that, the IDR strategy can run at least five-order faster while achieving comparable performance on total energy consumption of the QP-based method. Compared to the GA-based method, the IDR strategy can run at least three-order faster while achieving comparable (or even better) performance on total energy consumption.

Original languageEnglish
Title of host publication2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs
StatePublished - 25 Jul 2012
Event2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, Taiwan
Duration: 23 Apr 201225 Apr 2012

Publication series

Name2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

Conference

Conference2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
CountryTaiwan
CityHsinchu
Period23/04/1225/04/12

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    Liao, C. H., & Wen, H. P. (2012). Performance validation of dynamic-remapping-based task scheduling on 3D multi-core processors. In 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers [6212656] (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). https://doi.org/10.1109/VLSI-DAT.2012.6212656