Performance-preserved analog routing methodology via wire load reduction

Hao Yu Chi, Hwa Yi Tseng, Chien-Nan Liu, Hung-Ming Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Analog layout automation is a popular research direction in recent years to raise the design productivity. However, the research on this topic is still not well accepted by analog designers because notable performance loss often exists in tool-generated layout. Most previous works focus on layout placement problem and route the nets implicitly by typical digital routing methodology. This routing approach can solve the net crossing issue easily, but requires a lot of extra vias to connect the horizontal and vertical lines, which significantly increases the wire loads and reduces the circuit performance. In the proposed analog routing flow, we try to route each net with minimum layer changing and consider the wire length simultaneously. In other words, wire load is used as the optimization goal instead of using wire length only to keep the circuit performance after laying out the design. As demonstrated on several cases, this approach significantly reduces the wire load and keeps the similar circuit performance as in manual works.

Original languageEnglish
Title of host publicationASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages482-487
Number of pages6
ISBN (Electronic)9781509006021
DOIs
StatePublished - 20 Feb 2018
Event23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018 - Jeju, Korea, Republic of
Duration: 22 Jan 201825 Jan 2018

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2018-January

Conference

Conference23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018
CountryKorea, Republic of
CityJeju
Period22/01/1825/01/18

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    Chi, H. Y., Tseng, H. Y., Liu, C-N., & Chen, H-M. (2018). Performance-preserved analog routing methodology via wire load reduction. In ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings (pp. 482-487). (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2018-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2018.8297370