Performance of Super-Critical Strained-Si Directly on Insulator (SC-SSOI) CMOS based on high-performance PD-SOI technology

A. V.Y. Thean*, T. White, M. Sadaka, L. McCormick, M. Ramon, R. Mora, P. Beckage, M. Canonico, X. D. Wang, S. Zollner, S. Murphy, V. Van Der Pas, M. Zavala, R. Noble, O. Zia, L. G. Kang, V. Kolagunta, N. Cave, J. Cheek, M. MendicinoB. Y. Nguyen, M. Orlowski, S. Venkatesan, J. Mogab, H. Chang, Y. H. Chiu, H. C. Tuan, Y. C. See, M. S. Liang, Y. C. Sun, I. Cayrefourcq, F. Metral, M. Kennard, C. Mazure

*Corresponding author for this work

Research output: Contribution to journalConference article

20 Scopus citations

Abstract

This paper describes the performance of multiple-VT, Triple-gate oxide SC-SSOI CMOS realized with Freescale's high-performance Silicon-On-Insulator (HiPerMOS-SOI) and SOITEC's advanced wafer-bonding technology. The thermal stability of wafer-bonded strained substrate, the beneficial impact of biaxial strain on gate-leakage and SC-SSOI enhanced SRAM bitcell operation are demonstrated for the first time. In-addition, the important scaling issues due to parasitic resistance and channel strain engineering are identified.

Original languageEnglish
Article number1469242
Pages (from-to)134-135
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
Volume2005
DOIs
StatePublished - 2005
Event2005 Symposium on VLSI Technology - Kyoto, Japan
Duration: 14 Jun 200514 Jun 2005

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    Thean, A. V. Y., White, T., Sadaka, M., McCormick, L., Ramon, M., Mora, R., Beckage, P., Canonico, M., Wang, X. D., Zollner, S., Murphy, S., Van Der Pas, V., Zavala, M., Noble, R., Zia, O., Kang, L. G., Kolagunta, V., Cave, N., Cheek, J., ... Mazure, C. (2005). Performance of Super-Critical Strained-Si Directly on Insulator (SC-SSOI) CMOS based on high-performance PD-SOI technology. Digest of Technical Papers - Symposium on VLSI Technology, 2005, 134-135. [1469242]. https://doi.org/10.1109/.2005.1469242