This paper describes the performance of multiple-VT, Triple-gate oxide SC-SSOI CMOS realized with Freescale's high-performance Silicon-On-Insulator (HiPerMOS-SOI) and SOITEC's advanced wafer-bonding technology. The thermal stability of wafer-bonded strained substrate, the beneficial impact of biaxial strain on gate-leakage and SC-SSOI enhanced SRAM bitcell operation are demonstrated for the first time. In-addition, the important scaling issues due to parasitic resistance and channel strain engineering are identified.
|Number of pages||2|
|Journal||Digest of Technical Papers - Symposium on VLSI Technology|
|State||Published - 2005|
|Event||2005 Symposium on VLSI Technology - Kyoto, Japan|
Duration: 14 Jun 2005 → 14 Jun 2005