Performance improvement of polycrystalline silicon nanowire thin-film transistors by a high-k capping layer

Ko H. Lee; Hsing H. Hsu; Horng-Chih Lin; Tiao Yuan Huang

doi:10.1143/JJAP.48.021203

Performance improvement of polycrystalline silicon nanowire thin-film transistors by a high-k capping layer

Ko H. Lee^*, Hsing H. Hsu, Horng-Chih Lin, Tiao Yuan Huang

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

In this work, a novel polycrystalline silicon (poly-Si) nanowire thin-film transistor (NW-TFT) with side-gated configuration and a high-k material capping was fabricated and characterized. It was found that the gate fringing field effect via the high-k passivation layer can effectively improve the device performance in terms of higher ON current, larger ON/OFF current ratio, and steeper subthreshold slope (SS). The drain-induced barrier lowering (DIBL) effect is also effectively suppressed owing to better gate control.

Original language	English
Article number	021203
Journal	Japanese journal of applied physics
Volume	48
Issue number	2
DOIs	https://doi.org/10.1143/JJAP.48.021203
State	Published - 1 Feb 2009

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abstract = "In this work, a novel polycrystalline silicon (poly-Si) nanowire thin-film transistor (NW-TFT) with side-gated configuration and a high-k material capping was fabricated and characterized. It was found that the gate fringing field effect via the high-k passivation layer can effectively improve the device performance in terms of higher ON current, larger ON/OFF current ratio, and steeper subthreshold slope (SS). The drain-induced barrier lowering (DIBL) effect is also effectively suppressed owing to better gate control.",

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AB - In this work, a novel polycrystalline silicon (poly-Si) nanowire thin-film transistor (NW-TFT) with side-gated configuration and a high-k material capping was fabricated and characterized. It was found that the gate fringing field effect via the high-k passivation layer can effectively improve the device performance in terms of higher ON current, larger ON/OFF current ratio, and steeper subthreshold slope (SS). The drain-induced barrier lowering (DIBL) effect is also effectively suppressed owing to better gate control.

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