Abstract
In this work, a novel polycrystalline silicon (poly-Si) nanowire thin-film transistor (NW-TFT) with side-gated configuration and a high-k material capping was fabricated and characterized. It was found that the gate fringing field effect via the high-k passivation layer can effectively improve the device performance in terms of higher ON current, larger ON/OFF current ratio, and steeper subthreshold slope (SS). The drain-induced barrier lowering (DIBL) effect is also effectively suppressed owing to better gate control.
Original language | English |
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Article number | 021203 |
Journal | Japanese journal of applied physics |
Volume | 48 |
Issue number | 2 |
DOIs | |
State | Published - 1 Feb 2009 |