Performance improvement of polycrystalline silicon nanowire thin-film transistors by a high-k capping layer

Ko H. Lee*, Hsing H. Hsu, Horng-Chih Lin, Tiao Yuan Huang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

In this work, a novel polycrystalline silicon (poly-Si) nanowire thin-film transistor (NW-TFT) with side-gated configuration and a high-k material capping was fabricated and characterized. It was found that the gate fringing field effect via the high-k passivation layer can effectively improve the device performance in terms of higher ON current, larger ON/OFF current ratio, and steeper subthreshold slope (SS). The drain-induced barrier lowering (DIBL) effect is also effectively suppressed owing to better gate control.

Original languageEnglish
Article number021203
JournalJapanese journal of applied physics
Volume48
Issue number2
DOIs
StatePublished - 1 Feb 2009

Fingerprint Dive into the research topics of 'Performance improvement of polycrystalline silicon nanowire thin-film transistors by a high-k capping layer'. Together they form a unique fingerprint.

Cite this