Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers

Chia Chen Lin, Yi Jui Wu, Wei Xiang You, Pin Su*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this work, with the aid of a short-channel SPICE model, we evaluate the circuit performance of 2D negative-capacitance FETs (2D-NCFETs) considering the impact of spacers. Although high-k spacer may introduce parasitic capacitance, our study indicates that using higher-k spacer may improve the circuit performance for 2D-NCFETs due to the enhanced negative-capacitance effects (NC effects). In addition, considering the NC amplified gate capacitance, the intrinsic delay of 2D-NCFETs is still better than that of 2DFETs, especially for pass-transistor logic (PTL).

Original languageEnglish
Title of host publication2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages62-63
Number of pages2
ISBN (Electronic)9781728142326
DOIs
StatePublished - Aug 2020
Event2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 - Hsinchu, Taiwan
Duration: 10 Aug 202013 Aug 2020

Publication series

Name2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

Conference

Conference2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
CountryTaiwan
CityHsinchu
Period10/08/2013/08/20

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