Performance evaluation of inter-processor communication for an embedded heterogeneous multi-core processor

Shiao-Li Tsao*, Sung Yuan Lee

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

Embedded systems often use a heterogeneous multi-core processor to improve performance and energy efficiency. This multi-core processor is composed of a general purpose processor (GPP), which manages the program flow and I/O, and a digital signal processor (DSP), which processes mass data. An inter-processor communication (IPC) mechanism is thus required to exchange data between a GPP and a DSP. This paper uses comprehensive experiments to evaluate the IPC performance of an embedded heterogeneous multi-core processor under different design strategies. We further develop the IPC performance model and suggest dynamic adjustment of IPC strategies under environmental parameters and system resource constraints. Based on the results and findings, we improve the IPC performance of a voice over IP (VoIP) phone. Experimental results demonstrate that the GPP workload decreases significantly by 35% without sacrificing the functionalities and voice quality of the VoIP system. Moreover, we apply the concept of dynamic adjustment of IPC strategies to an embedded media gateway. The simulation results demonstrate that the dynamic IPC strategy can considerably improve the system performance of the media gateway compared with the static IPC design approach.

Original languageEnglish
Pages (from-to)537-554
Number of pages18
JournalJournal of Information Science and Engineering
Volume28
Issue number3
DOIs
StatePublished - 1 May 2012

Keywords

  • Embedded system
  • Heterogeneous multi-core processor
  • Inter-processor communication
  • Multi-core
  • Performance evaluation

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