Performance Enhancement of a Novel P-type Junctionless Transistor Using a Hybrid Poly-Si Fin Channel

Ya-Chi Cheng, Hung Bin Chen, Chi-Shen Shao, Jun-Ji Su, Yung-Chun Wu, Chun-Yen Chang, Ting-Chang Chang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

The hybrid poly-Si fin channel junctionless (JL) field-effect transistors (FET) are fabricated first. This novel devices show stable temperature/reliability characteristics, and excellent electrical performances in terms of a steep SS (64mV/dec), a high I-on/I-off current ratio (>10(7)) and a small DIBL (3mV/V) by reducing the effective channel thickness that is caused by the hybrid P+ channel and n-type substrate (hybrid P/N) junction. In addition, the novel P/N JL-TFT shows smaller series resistance and less current crowding than convectional JL-TFT with ultra-thin channel. Furthermore, our device can be supported by simulated results using technology computer-aided design (TCAD) simulation. Hence, the proposed hybrid P/N JL-TFTs are highly promising for future further scaling.
Original languageEnglish
Title of host publication60th Annual IEEE International Electron Devices Meeting (IEDM)
DOIs
StatePublished - 2014

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