Performance enhancement in double-gated poly-Si nanowire transistors with reduced nanowire channel thickness

Horng-Chih Lin*, Wei Chen Chen, Tiao Yuan Huang, Chuan Ding Lin

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

28 Scopus citations

Abstract

A new method is proposed and successfully demonstrated for the fabrication of polycrystalline silicon (poly-Si) nanowire (NW) transistors with rectangular-shaped NW channels and two independent gates. The two independently controllable gates allow higher flexibility in device operation and provide a unique insight into the conduction mechanism of the NW device. Our results indicate that dramatic performance enhancement is feasible when the thickness of the NW channel is sufficiently thin, and the two conduction channels in the NW structure are operating simultaneously.

Original languageEnglish
Pages (from-to)644-646
Number of pages3
JournalIEEE Electron Device Letters
Volume30
Issue number6
DOIs
StatePublished - 30 Apr 2009

Keywords

  • Double gate
  • Nanowire (NW)
  • Polycrystalline silicon (poly-Si)

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