Performance constraints aware voltage Islands generation in SoC floorplan design

Ming Ching Lu*, Meng Chen Wu, Hung Ming Chen, Hui Ru Jiang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

Using voltage island methodology to reduce power consumption for System-on-a-Chip (SoC) designs has become more and more popular recently. Currently this approach has been considered either in system-level architecture or post-placement stage. Since hierarchical design and reusable intellectual property (IP) are widely used, it is necessary to optimize floorplanning/ placement methodology considering voltage islands generation to solve power and critical path delay problems. In this paper, we propose a floorplanning methodology considering voltage islands generation and performance constraints. Our method is flexible and can be extended to hierarchical design. The experimental results on some MCNC benchmarks show that our method is effective in meeting performance constraints and simultaneously considers the tradeoff between power routing cost and the assignment of supply voltage in modules.

Original languageEnglish
Title of host publication2006 IEEE International Systems-on-Chip Conference, SOC
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages211-214
Number of pages4
ISBN (Print)0780397819, 9780780397811
DOIs
StatePublished - 1 Jan 2006
Event2006 IEEE International Systems-on-Chip Conference, SOC - Austin, TX, United States
Duration: 24 Sep 200627 Sep 2006

Publication series

Name2006 IEEE International Systems-on-Chip Conference, SOC

Conference

Conference2006 IEEE International Systems-on-Chip Conference, SOC
CountryUnited States
CityAustin, TX
Period24/09/0627/09/06

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