Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning

Meng Chen Wu*, Ming Ching Lu, Hung-Ming Chen, Jing Yang Jou

*Corresponding author for this work

Research output: Contribution to journalArticle

2 Scopus citations

Abstract

Using voltage island methodology to reduce power consumption for System-on-a-Chip (SoC) designs has become more and more popular recently. Currently this approach has been considered either in system-level architecture or postplacement stage. Since hierarchical design and reusable intellectual property (IP) are widely used, it is necessary to optimize floorplanning/ placement methodology considering voltage islands generation to solve power and critical path delay problems. In this article, we propose a floorplanning methodology considering voltage islands generation and performance constraints. Our method is flexible and can be extended to hierarchical design. The experimental results on some MCNC benchmarks show that our method is effective in meeting performance constraints and can simultaneously consider the tradeoff between power routing cost and total power dissipation.

Original languageEnglish
Article number3
JournalACM Transactions on Design Automation of Electronic Systems
Volume15
Issue number1
DOIs
StatePublished - 1 Dec 2009

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