Performance and V dd scaling in deep submicrometer CMOS

Kai Chen*, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalArticle

28 Scopus citations

Abstract

Analytical models on metal-oxide-semiconductor field-effect transistor (MOSFET) scaling and complementary (CMOS) ring oscillator performance developed recently are applied to revisit CMOS design guidelines because those based on the basic long channel model are obsolete. Handy and empirical equations for deep submicrometer MOSFET drain saturation current are developed. The differences between the basic long channel model and the accurate deep submicrometer MOSFET current model are highlighted. Design guidelines on V th and V dd scaling as well as interconnect loading effects based on the accurate models are presented.

Original languageEnglish
Pages (from-to)1586-1589
Number of pages4
JournalIEEE Journal of Solid-State Circuits
Volume33
Issue number10
DOIs
StatePublished - 1 Oct 1998

Keywords

  • CMOS
  • Deep submicrometer device
  • Low-power CMOS
  • Scaling

Fingerprint Dive into the research topics of 'Performance and V <sub>dd</sub> scaling in deep submicrometer CMOS'. Together they form a unique fingerprint.

  • Cite this