Performance and Stability Benchmarking of Monolithic 3-D Logic Circuits and SRAM Cells with Monolayer and Few-Layer Transition Metal Dichalcogenide MOSFETs

Chang Hung Yu, Pin Su*, Ching Te Chuang

*Corresponding author for this work

Research output: Contribution to journalArticle

4 Scopus citations

Abstract

For the first time, considering the architecture of monolithic 3-D integration, we evaluate and benchmark the performance of 3-D logic circuits and stability/performance of 3-D 6T SRAM cells with monolayer and few-layer transition metal dichalcogenide (TMD) devices based on ITRS 2028 (5.9 nm) technology node. The impact of random variations on the cell stability is also investigated. With the possibility of adopting monolayer or few-layer TMDs for nFET-A nd pFET-tiers enabled by monolithic 3-D integration, this paper indicates that the trilayer TMD device may substantially degrade the performance of 3-D logic circuits in spite of its higher mobility. This paper also reveals that stacking the monolayer pFET-tier over the bilayer nFET-tier may provide better nominal stability and read/write performance for 6T superthreshold SRAM compared with the planar technology, whereas the optimum 3-D configuration for near-/sub-threshold operations appears to be the monolayer pFET-tier over the monolayer nFET-tier. Besides the 6T cell structure, 8T SRAM cells are also investigated with monolithic 3-D integration for near-threshold/subthreshold operation. The monolayer nFET-tier over the bilayer pFET-tier configuration is shown to be the optimum 3-D 8T near-threshold/subthreshold cell design.

Original languageEnglish
Article number7891052
Pages (from-to)2445-2451
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume64
Issue number5
DOIs
StatePublished - 1 May 2017

Keywords

  • 2-D materials
  • logic circuits
  • monolithic 3-D integration
  • SRAM cells
  • transition metal dichalcogenide (TMD)

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