Peak wake-up current estimation at gate-level with standard library information

Mu Shun Matt Lee*, Yi Chu Liu, Wan Rong Wu, Chien-Nan Liu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

In power gating designs, it is important to estimate the peak wake-up current at the design stages to avoid possible power issues.In this paper, an analytical approach is proposed toestimate the peak wake-up current of a given wake-up input pattern at gate level. The required information of the proposed approach can be directly obtained from existing library information without extra characterization, which can be easily inserted into existing EDA flow with little overhead.The extra effects of power switches on the current waveformsare also considered in the proposed approach, which significantly improve the estimation accuracy as demonstrated in the experiments.

Original languageEnglish
Title of host publication2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs
StatePublished - 25 Jul 2012
Event2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, Taiwan
Duration: 23 Apr 201225 Apr 2012

Publication series

Name2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

Conference

Conference2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
CountryTaiwan
CityHsinchu
Period23/04/1225/04/12

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    Lee, M. S. M., Liu, Y. C., Wu, W. R., & Liu, C-N. (2012). Peak wake-up current estimation at gate-level with standard library information. In 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers [6212629] (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). https://doi.org/10.1109/VLSI-DAT.2012.6212629