Partial-SOI Isolation Structure for Reduced Bipolar Transistor Parasitics

Joachim N. Burghartz, John D. Cressler, J. James, W. Warnock, R. C. McIntosh, K. A. Jenkins, J. Y.C. Sun, James H. Comfort, Johannes Stork, C. L. Stanis, Wai Lee, D. D. Danner

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A novel bipolar isolation structure with capability of significantly reducing collector-base capacitance and base resistance is presented. Partial SOI, with SOI surrounding the collector opening, can be used to reduce the collector window width in combination with any emitter-base self-aligned bipolar device structure, and in particular for device structures that feature sublithographic emitter width. Near-ideal transistor Gummel characteristics and a minimum ECL gate delay of 24 ps have been achieved with a nonoptimized lateral device layout, and simulations suggest that sub-20-ps delay at reduced switch current will be possible by using the optimized partial-SOI isolation structure.

Original languageEnglish
Pages (from-to)424-426
Number of pages3
JournalIEEE Electron Device Letters
Issue number8
StatePublished - Aug 1992

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    Burghartz, J. N., Cressler, J. D., James, J., Warnock, W., McIntosh, R. C., Jenkins, K. A., Sun, J. Y. C., Comfort, J. H., Stork, J., Stanis, C. L., Lee, W., & Danner, D. D. (1992). Partial-SOI Isolation Structure for Reduced Bipolar Transistor Parasitics. IEEE Electron Device Letters, 13(8), 424-426.