Parameterized and low power DSP core for embedded systems

Ya Lan Tsao*, Ming Hsuan Tan, Jun Xian Teng, Shyh-Jye Jou

*Corresponding author for this work

Research output: Contribution to journalConference article

5 Scopus citations

Abstract

Conventional ASIC designs are hard to be customized. Therefore DSP core-based ASIC design has potentially large payoff. This approach not only supports improved performance but also shortens the time-to-market. An Embedded DSP was proposed and for better performance and flexibility we design a parameterized and low power DSP core generator, Dual MAC unit, sub-word multiplier, and some function-specific blocks are adapted to accelerate applications of communication system. The gray code addressing mode, pipeline sharing and advanced hardware looping are designed to reduce power consumption in architecture level. The generator uses graphical user interface (GUI) and can generate synthesizable verilog code of the embedded DSP core according to user's specification.

Original languageEnglish
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume5
DOIs
StatePublished - 14 Jul 2003
EventProceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand
Duration: 25 May 200328 May 2003

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