Parallelism of circuit simulation on array processor

Shyh-Jye Jou*, Chein Wei Jen, Wen Zen Shen

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

Abstract

The intrinsic parallelism of circuit simulation techniques, especially the relaxation-based electrical simulation technique, is analyzed by the dependence graph (DG) representation. The results show that many proposed parallel schemes are the different mappings of these DGs. The hardware array processor architectures for an event-driven MOS timing simulator, EMOTA, are proposed and discussed.

Original languageEnglish
Pages (from-to)2725-2728
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume5
DOIs
StatePublished - 1 Dec 1991
Event1991 IEEE International Symposium on Circuits and Systems Part 4 (of 5) - Singapore, Singapore
Duration: 11 Jun 199114 Jun 1991

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