In order to improve the speed limitation of serial scrambler, we propose a new parallel scrambler architecture and circuit to overcome the limitation of serial scrambler. A very systematic parallel scrambler design methodology is first proposed. The critical path delay is only one D-register and one XOR gate of two inputs. Thus, it is superior to other proposed circuits in high-speed applications. A new DET D-register with embedded XOR operation is used as a basic circuit block of the parallel scram-bler. Measurement results show the proposed parallel scrambler can operate in 40 Gbps with 16 outputs in TSMC 0.18-μm CMOS process.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|State||Published - 6 Jul 2006|
- Parallel scrambler