Parallel Scrambler for High-Speed Applications

Chih Hsien Lin, Chih Ning Chen, You Jiun Wang, Ju Yuan Hsiac, Shyh-Jye Jou

Research output: Contribution to journalArticle

10 Scopus citations

Abstract

In order to improve the speed limitation of serial scrambler, we propose a new parallel scrambler architecture and circuit to overcome the limitation of serial scrambler. A very systematic parallel scrambler design methodology is first proposed. The critical path delay is only one D-register and one XOR gate of two inputs. Thus, it is superior to other proposed circuits in high-speed applications. A new DET D-register with embedded XOR operation is used as a basic circuit block of the parallel scram-bler. Measurement results show the proposed parallel scrambler can operate in 40 Gbps with 16 outputs in TSMC 0.18-μm CMOS process.

Original languageEnglish
Pages (from-to)558-562
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume53
Issue number7
DOIs
StatePublished - 6 Jul 2006

Keywords

  • Parallel scrambler
  • register
  • XOR

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