P4-TPG: Accelerating deterministic parallel test pattern generation by preemptive, proactive, and preventive schedulings

Louis Y.Z. Lin*, Charles Chia Hao Hsu, Charles H.P. Wen

*Corresponding author for this work

Research output: Contribution to journalArticle

Abstract

According to the prior research, a deterministic parallel test pattern generation (TPG) engine was realized and generated the same test pattern set the serial automatic test pattern generation does during acceleration. However, for retaining the determinism, tremendous idle time is observed when different tasks (either dependent or independent) were synchronized among threads. Therefore, a new deterministic parallel TPG engine called P4-TPG is developed and incorporates preemptive, proactive, and preventive schedulings to further save/reuse the idle time during acceleration. In P4-TPG, preemptive scheduling first modifies the thread flow and brings forward, as many latter tasks as possible, to the idle time. Next, proactive scheduling inserts prospective TPG tasks of unprocessed faults to the remaining idle time and increases the overall utilization of threads. Last, preventive scheduling dynamically skips faults incompatible with the working pattern per thread and shortens the fault list during fault compaction. The experimental results show that P4-TPG not only generates the same test pattern set as the serial TPG does but also achieves averagely 10.36 × speedups, is 96.6% better than the prior research, using 12 threads on 18 benchmark circuits.

Original languageEnglish
Article number8594557
Pages (from-to)6816-6830
Number of pages15
JournalIEEE Access
Volume7
DOIs
StatePublished - 1 Jan 2019

Keywords

  • deterministic
  • dynamic compaction
  • Parallel ATPG
  • test inflation

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