MOSFET with EOT below 0.37 nm has been achieved with La2O 3 gate dielectric by realizing direct contact on Si. A sufficient increase in drain current has been observed while scaling the EOT from 0.48 to 0.37 nm. Therefore, continuous scaling of EOT below 0.5 nm is still effective for further improvement in device performance. Moreover, the EOT increment by La-silicate formation after high temperature annealing can be well suppressed under control of oxygen by selecting a metal gate.
|Title of host publication||ECS Transactions - ULSI Process Integration 6|
|Number of pages||5|
|State||Published - 2009|
|Event||ULSI Process Integration 6 - 216th Meeting of the Electrochemical Society - Vienna, Austria|
Duration: 4 Oct 2009 → 9 Oct 2009
|Conference||ULSI Process Integration 6 - 216th Meeting of the Electrochemical Society|
|Period||4/10/09 → 9/10/09|