Overwhelming the 0.5 nm EOT level for CMOS gate dielectric

K. Kakushima*, P. Ahmet, H. Iwai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

MOSFET with EOT below 0.37 nm has been achieved with La2O 3 gate dielectric by realizing direct contact on Si. A sufficient increase in drain current has been observed while scaling the EOT from 0.48 to 0.37 nm. Therefore, continuous scaling of EOT below 0.5 nm is still effective for further improvement in device performance. Moreover, the EOT increment by La-silicate formation after high temperature annealing can be well suppressed under control of oxygen by selecting a metal gate.

Original languageEnglish
Title of host publicationECS Transactions - ULSI Process Integration 6
Pages171-175
Number of pages5
Edition7
DOIs
StatePublished - 2009
EventULSI Process Integration 6 - 216th Meeting of the Electrochemical Society - Vienna, Austria
Duration: 4 Oct 20099 Oct 2009

Publication series

NameECS Transactions
Number7
Volume25
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Conference

ConferenceULSI Process Integration 6 - 216th Meeting of the Electrochemical Society
CountryAustria
CityVienna
Period4/10/099/10/09

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