Overview on the design of low-leakage power-rail ESD clamp circuits in nanoscale CMOS processes

Federico A. Altolaguirre*, Ming-Dou Ker

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The circuit techniques to overcome the gate leakage issue in advanced nanoscale CMOS technologies are presented. These circuit techniques can reduce the total leakage current from the high value of 21μA in the traditional power-rail ESD clamp circuit down to only 96nA (under 1 Volt operating voltage, at room temperature) while maintaining very high ESD robustness (as high as 8kV HBM and 800V MM) in a 65-nm CMOS technology.

Original languageEnglish
Title of host publication2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2011
Pages108-112
Number of pages5
StatePublished - 5 Oct 2011
Event2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2011 - Buenos Aires, Argentina
Duration: 6 Aug 201113 Aug 2011

Publication series

Name2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2011

Conference

Conference2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2011
CountryArgentina
CityBuenos Aires
Period6/08/1113/08/11

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