Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: Design concept and circuit implementations

Ming-Dou Ker*, Kun Hsien Lin

*Corresponding author for this work

Research output: Contribution to journalArticle

23 Scopus citations

Abstract

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nano-scale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O. interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification and analysis of ESD protection designs for mixed-voltage I/O interfaces, and the designs of high-voltage-tolerant power-rail ESD clamp circuit are presented and discussed.

Original languageEnglish
Pages (from-to)235-246
Number of pages12
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume53
Issue number2
DOIs
StatePublished - 1 Dec 2006

Keywords

  • ESD protection design
  • Electrostatic discharge (ESD)
  • Gate-oxide reliability
  • High-voltage tolerant
  • Mixed-voltage I/o interfaces
  • Power-rail ESD clamp circuit

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