Overview and design of mixed-voltage I/O buffers with low-voltage thin-oxide CMOS transistors

Ming-Dou Ker*, Shih Lun Chen, Chia Sheng Tsai

*Corresponding author for this work

Research output: Contribution to journalReview articlepeer-review

50 Scopus citations

Abstract

Overview on the prior designs of the mixed-voltage I/O buffers is provided in this work. A new 2.5/5-V mixed-voltage I/O buffer realized with only thin gate-oxide devices is proposed. The new proposed mixed-voltage I/O buffer with simpler dynamic n-well bias circuit and gate-tracking circuit can prevent the undesired leakage current paths and the gate-oxide reliability problem, which occur in the conventional CMOS I/O buffer. The new mixed-voltage I/O buffer has been fabricated and verified in a 0.25-μm CMOS process to serve 2.5/5-V I/O interface. Besides, another 2.5/5-V mixed-voltage I/O buffer without the subthreshold leakage problem for high-speed applications is also presented in this work. The speed, power consumption, area, and noise among these mixed-voltage I/O buffers are also compared and discussed. The new proposed mixed-voltage I/O buffers can be easily scaled toward 0.18- μm (or below) CMOS processes to serve other mixed-voltage I/O interfaces, such as 1.8/3.3-V interface.

Original languageEnglish
Pages (from-to)1934-1945
Number of pages12
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume53
Issue number9
DOIs
StatePublished - 1 Sep 2006

Keywords

  • Gate-oxide reliability
  • Gate-tracking circuit
  • Interface
  • Mixed-voltage I/O buffer

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