We present a model for the on-state resistance of power vertical, double-diffused MOS (VDMOS) transistors with emphasis on cell layout optimization and supporting experimental data. Essentially the same minimum Ron can be achieved using any of six different cellular cell geometries including square and hexagonal cells. Specifically, the on-resistances of all cellular designs are essentially identical if they have the same p-well width and the same ratio of well area to cell area. Cellular designs yield lower on-resistance than linear-cell designs unless the latter, through clever layout perhaps, allows at least 1.6 times smaller well width than the former. Design examples and experiments illustrate a simple optimization procedure, which starts with choosing the minimum p-well width and depth compatible with production technology and then finding the optimum spacing between the p-wells.