Optimizing quarter and sub-quarter micron cmos circuit speed considering interconnect loading effects

Kai Chen*, Chen-Ming Hu, Peng Fang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

An experimentally confirmed accurate CMOS gate delay model is applied to the CMOS ring oscillators with interconnect loading. The optimum gate oxide thickness T ox should be chosen differently as interconnect loading varies. Guidelines in choosing optimum T ox for different interconnect loading, combined with channel length and power supply scaling, are obtained.

Original languageEnglish
Pages (from-to)1556-1558
Number of pages3
JournalIEEE Transactions on Electron Devices
Volume44
Issue number9
DOIs
StatePublished - 1 Dec 1997

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