Optimized poly-Si1-xGex-gate technology for dual gate CMOS application

Wen Chin Lee*, Tsu Jae King, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

12 Scopus citations


For deep submicron dual-gate CMOS application with poly-Si1-xGex gate technology, a Ge content of approximately 20% is the optimum choice in terms of short-channel effect (SCE) and poly-gate-depletion effect (PDE). It is demonstrated that poly-Si0.8Ge0.2-gated devices have the potential for alleviating the boron penetration problem without degrading gate oxide reliability as compared to poly-Si-gated devices.

Original languageEnglish
Pages (from-to)190-191
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
StatePublished - 1 Jan 1998
EventProceedings of the 1998 Symposium on VLSI Technology - Honolulu, HI, USA
Duration: 9 Jun 199811 Jun 1998

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