Optimization on MOS-triggered SCR structures for On-Chip ESD protection

Shih Hung Chen*, Ming-Dou Ker

*Corresponding author for this work

Research output: Contribution to journalArticle

14 Scopus citations

Abstract

MOS-triggered silicon-controlled rectifier (SCR) devices have been reported to achieve efficient on-chip electrostatic discharge (ESD) protection in deep-submicrometer CMOS technology. The channel length of the embedded MOS transistor in the MOS-triggered SCR device dominates the trigger mechanism and current distribution to govern the trigger voltage, holding voltage, on resistance, second breakdown current, and ESD robustness of the MOS-triggered SCR device. The embedded MOS transistor in the MOS-triggered SCR device should be optimized to achieve the most efficient ESD protection in advanced CMOS technology. In addition, the layout style of the embedded MOS transistor can be adjusted to improve the MOS-triggered SCR device for ESD protection.

Original languageEnglish
Pages (from-to)1466-1472
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume56
Issue number7
DOIs
StatePublished - 5 Jun 2009

Keywords

  • ESD protection
  • Electrostatic discharge (ESD)
  • Silicon-controlled rectifiers (SCRs)

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