Optimization on layout style of ESD protection diode for radio-frequency front-end and high-speed I/O interface circuits

Chih Ting Yeh*, Ming-Dou Ker, Yung Chih Liang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

24 Scopus citations

Abstract

The diode operated in forward-biased condition has been widely used as an effective on-chip electrostatic discharge (ESD) protection device at radio-frequency (RF) front-end and high-speed input/output (I/O) pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes drawn in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The measured results confirmed that they can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the stripe and waffle diodes, especially for the diodes drawn in the hollow layout style. Therefore, the signal degradation of RF and high-speed transmission can be reduced because of smaller parasitic capacitance from the new proposed diodes.

Original languageEnglish
Article number5415645
Pages (from-to)238-246
Number of pages9
JournalIEEE Transactions on Device and Materials Reliability
Volume10
Issue number2
DOIs
StatePublished - 1 Jun 2010

Keywords

  • Diode
  • Electrostatic discharge (ESD)
  • Layout
  • Radio-frequency (RF)

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